Cadence SH/BJ招聘 Senior Design Engineer-front-end

铿腾电子

Cadence SH/BJ招聘 Senior Design Engineer-front-end

工作地点：上海/北京

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If you have interest, PLS send your update CV to zhangyl@cadence.com

Title: Senior design engineer

  

Position Description:

•In charge of IP and SOC logic design, verification and Implementation.

•Daily duties include: Digital IC micro-architecture, RTL coding, Logic Synthesis, Function Verification, DFT, and Static Timing Analysis.

•HDL language Knowledge, like verilog or vhdl is necessary.

•C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.

•Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical and complex topics.

•Excellent communication skills and the uncanny ability in a cooperative team environment are required.

•Self-motivated, result-oriented, can take ownership and follow-through on tasks.

Position Requirements:

Essential Qualifications:

•Master degree or above

•Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology or equivalent

•Ability to work effectively alone or as well as in the team.

•Essential that the individual demonstrates strong communication, verbal and written

•Requires good communication skills in English.

Desirable Qualifications:

•Good at any following skill sets: ASIC design, FPGA design, Computer architecture, SOC design based on ARM/MIPS.

•Experience of DDR